TY - GEN
T1 - A CMOS imager with focal plane compression
AU - Leon-Salas, Walter D.
AU - Balkir, Sina
AU - Sayood, Khalid
AU - Hoffman, Michael W.
AU - Schemm, Nathan
PY - 2006
Y1 - 2006
N2 - A focal plane video compression integrated circuit is presented. The design consists of a 128 × 128 pixel array and a bank of column-level processors. Each one of the column-level processors performs the tasks of image decorrelation, quantization, and entropy encoding. The chip provides at its output a compressed bit stream. The integration of the quantizer and the entropy encoder at the column level is possible by sharing circuitry between a single-slope analog-to-digital converter and a Golomb-Rice entropy encoder. In addition, the design includes a low-complexity algorithm for the adaptation of the Golomb-Rice coder to the statistics of the video signal. The design has been fully verified through simulations and has been implemented in a 0.35 μm CMOS technology. The chip layout occupies an area of 7 × 5 mm2.
AB - A focal plane video compression integrated circuit is presented. The design consists of a 128 × 128 pixel array and a bank of column-level processors. Each one of the column-level processors performs the tasks of image decorrelation, quantization, and entropy encoding. The chip provides at its output a compressed bit stream. The integration of the quantizer and the entropy encoder at the column level is possible by sharing circuitry between a single-slope analog-to-digital converter and a Golomb-Rice entropy encoder. In addition, the design includes a low-complexity algorithm for the adaptation of the Golomb-Rice coder to the statistics of the video signal. The design has been fully verified through simulations and has been implemented in a 0.35 μm CMOS technology. The chip layout occupies an area of 7 × 5 mm2.
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M3 - Conference contribution
AN - SCOPUS:34547249295
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 3570
EP - 3573
BT - ISCAS 2006
T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Y2 - 21 May 2006 through 24 May 2006
ER -