A CMOS imager with focal plane compression

Walter D. Leon-Salas, Sina Balkir, Khalid Sayood, Michael W. Hoffman, Nathan Schemm

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

A focal plane video compression integrated circuit is presented. The design consists of a 128 × 128 pixel array and a bank of column-level processors. Each one of the column-level processors performs the tasks of image decorrelation, quantization, and entropy encoding. The chip provides at its output a compressed bit stream. The integration of the quantizer and the entropy encoder at the column level is possible by sharing circuitry between a single-slope analog-to-digital converter and a Golomb-Rice entropy encoder. In addition, the design includes a low-complexity algorithm for the adaptation of the Golomb-Rice coder to the statistics of the video signal. The design has been fully verified through simulations and has been implemented in a 0.35 μm CMOS technology. The chip layout occupies an area of 7 × 5 mm2.

Original languageEnglish (US)
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages3570-3573
Number of pages4
StatePublished - 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: May 21 2006May 24 2006

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

ConferenceISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/TerritoryGreece
CityKos
Period5/21/065/24/06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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