A CMOS imager with focal plane compression using predictive coding

Walter D. León-Salas, Sina Balkir, Khalid Sayood, Nathan Schemm, Michael W. Hoffman

Research output: Contribution to journalArticle

49 Scopus citations

Abstract

This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit. The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizer/coder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 μm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm × 5.96 mm which includes an 80 × 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

Original languageEnglish (US)
Article number4362102
Pages (from-to)2555-2572
Number of pages18
JournalIEEE Journal of Solid-State Circuits
Volume42
Issue number11
DOIs
StatePublished - Nov 2007

Keywords

  • Analog-digital conversion
  • CMOS image sensors
  • Data compression
  • Image coding
  • predictive coding

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    León-Salas, W. D., Balkir, S., Sayood, K., Schemm, N., & Hoffman, M. W. (2007). A CMOS imager with focal plane compression using predictive coding. IEEE Journal of Solid-State Circuits, 42(11), 2555-2572. [4362102]. https://doi.org/10.1109/JSSC.2007.907191