A small chip area 12-b 300MS/S Current Steering CMOS D/A converter based on a laminated-step layout technique

Byungseung Lee, Byungill Kim, Juneseok Lee, Sanghoon Hwang, Minkyu Song, Tad Wysocki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A 12-b 300MSPS Current-Steering DAC with 0.13um CMOS technology is presented. In order to reduce the chip area, a laminated-step layout technique is proposed. Based on this technique, the occupied DAC core size is only 0.26mm2 even in 12-b resolution. Further, a current auto-averaging technique, an output impedance enhancement circuit, and the novel latched switching cell logic are discussed to keep the desired 12-b DAC performance. The measured results are within ±1LSB for DNL. The measured SFDR is 70dB under Nyquist output frequency with 50mW power dissipation at 3.3V power supply.

Original languageEnglish (US)
Title of host publicationEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007
PublisherIEEE Computer Society
Pages882-885
Number of pages4
ISBN (Print)1424413427, 9781424413423
DOIs
StatePublished - 2007
EventEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007 - Seville, Spain
Duration: Aug 26 2007Aug 30 2007

Publication series

NameEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007

Other

OtherEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007
CountrySpain
CitySeville
Period8/26/078/30/07

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Electrical and Electronic Engineering

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    Lee, B., Kim, B., Lee, J., Hwang, S., Song, M., & Wysocki, T. (2007). A small chip area 12-b 300MS/S Current Steering CMOS D/A converter based on a laminated-step layout technique. In European Conference on Circuit Theory and Design 2007, ECCTD 2007 (pp. 882-885). [4529738] (European Conference on Circuit Theory and Design 2007, ECCTD 2007). IEEE Computer Society. https://doi.org/10.1109/ECCTD.2007.4529738