Abstract
We present a study of an experimental interconnection network in this paper. This architecture is based on ultra-high speed full-duplex serial links and columns of switches. The interconnection network places the outer columns of the switches in a connected binary tree topology while the innermost columns are linked point-to-point. Switches provide routing through the interconnection network. We have discussed the characteristics of SLIN in terms of organization, system design, performance measures, cost-effectiveness and load-balancing potential. Analytical and computer models of the SLIN architecture are designed to provide system performance measures. These measures are compared with other related interconnection network architectures. The results of the SLIN models suggest a promising cost/performance ratio, afar better link utilization, and inherently suitable for load balancing.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 287-299 |
| Number of pages | 13 |
| Journal | Computer Systems Science and Engineering |
| Volume | 11 |
| Issue number | 5 |
| State | Published - Sep 1996 |
Keywords
- Interconnection network
- Serial-link
- Shared memory
ASJC Scopus subject areas
- Control and Systems Engineering
- Theoretical Computer Science
- Computer Science(all)