Design for testability and test generation with two clocks

V. D. Agrawal, S. C. Seth, J. S. Deogun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations


Proposes a novel design for testability method that enhances the controllability of storage elements by use of additional clock lines. The scheme is applicable to synchronous circuits but is otherwise transparent to the designer. The associated area and speed penalties are minimal compared to scan based methods. However, a sequential ATPG system is necessary for test generation. The basic idea is to use independent clock lines to control disjoint groups of flip-flops. No cyclic path is permitted among the flip-flops of the same group. During testing, a selected group can be made to hold its state by disabling its clock lines. In the normal mode, all clock lines carry the same system clock signal. With the appropriate partitioning of flip-flops, the length of the vector sequence produced by the test generator for a fault is drastically reduced. An n-stage binary counter is used for experimental verification of reduction in test length by the proposed technique.

Original languageEnglish (US)
Title of host publicationVLSI Design 1991 - Digest of Papers - 4th CSI/IEEE International Symposium on VLSI Design
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)0818621257
StatePublished - 1991
Event4th CSI/IEEE International Symposium on VLSI Design, VLSI 1991 - New Delhi, India
Duration: Jan 4 1991Jan 8 1991

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667


Conference4th CSI/IEEE International Symposium on VLSI Design, VLSI 1991
CityNew Delhi

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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