TY - GEN
T1 - Design for testability and test generation with two clocks
AU - Agrawal, V. D.
AU - Seth, S. C.
AU - Deogun, J. S.
N1 - Publisher Copyright:
© 1991 IEEE.
PY - 1991
Y1 - 1991
N2 - Proposes a novel design for testability method that enhances the controllability of storage elements by use of additional clock lines. The scheme is applicable to synchronous circuits but is otherwise transparent to the designer. The associated area and speed penalties are minimal compared to scan based methods. However, a sequential ATPG system is necessary for test generation. The basic idea is to use independent clock lines to control disjoint groups of flip-flops. No cyclic path is permitted among the flip-flops of the same group. During testing, a selected group can be made to hold its state by disabling its clock lines. In the normal mode, all clock lines carry the same system clock signal. With the appropriate partitioning of flip-flops, the length of the vector sequence produced by the test generator for a fault is drastically reduced. An n-stage binary counter is used for experimental verification of reduction in test length by the proposed technique.
AB - Proposes a novel design for testability method that enhances the controllability of storage elements by use of additional clock lines. The scheme is applicable to synchronous circuits but is otherwise transparent to the designer. The associated area and speed penalties are minimal compared to scan based methods. However, a sequential ATPG system is necessary for test generation. The basic idea is to use independent clock lines to control disjoint groups of flip-flops. No cyclic path is permitted among the flip-flops of the same group. During testing, a selected group can be made to hold its state by disabling its clock lines. In the normal mode, all clock lines carry the same system clock signal. With the appropriate partitioning of flip-flops, the length of the vector sequence produced by the test generator for a fault is drastically reduced. An n-stage binary counter is used for experimental verification of reduction in test length by the proposed technique.
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U2 - 10.1109/ISVD.1991.185102
DO - 10.1109/ISVD.1991.185102
M3 - Conference contribution
AN - SCOPUS:85013621402
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 112
EP - 117
BT - VLSI Design 1991 - Digest of Papers - 4th CSI/IEEE International Symposium on VLSI Design
PB - IEEE Computer Society
T2 - 4th CSI/IEEE International Symposium on VLSI Design, VLSI 1991
Y2 - 4 January 1991 through 8 January 1991
ER -