Design of a 1.8V 8-bit 500MSPS Folding-interpolation CMOS A/D converter with a folder averaging technique

Dongjin Lee, Jaewon Song, Jongha Shin, Sanghoon Hwang, Minkyu Song, Tad Wysocki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500MSPS at 1.8V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.79mm 2 and it consumes about 200mW at 1.8V power supply. The DNL and INL are within ±0.6/±0.6LSB, respectively. The measured result of SNDR is 47.05dB.

Original languageEnglish (US)
Title of host publicationEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007
PublisherIEEE Computer Society
Pages356-359
Number of pages4
ISBN (Print)1424413427, 9781424413423
DOIs
StatePublished - 2007
Externally publishedYes
EventEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007 - Seville, Spain
Duration: Aug 26 2007Aug 30 2007

Publication series

NameEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007

Other

OtherEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007
Country/TerritorySpain
CitySeville
Period8/26/078/30/07

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Electrical and Electronic Engineering

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