Design of a 1.8V 8-bit 500MSPS Folding-interpolation CMOS A/D converter with a folder averaging technique

Dongjin Lee; Jaewon Song; Jongha Shin; Sanghoon Hwang; Minkyu Song; Tad Wysocki

doi:10.1109/ECCTD.2007.4529606

Design of a 1.8V 8-bit 500MSPS Folding-interpolation CMOS A/D converter with a folder averaging technique

Dongjin Lee, Jaewon Song, Jongha Shin, Sanghoon Hwang, Minkyu Song, Tad Wysocki

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500MSPS at 1.8V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.79mm ² and it consumes about 200mW at 1.8V power supply. The DNL and INL are within ±0.6/±0.6LSB, respectively. The measured result of SNDR is 47.05dB.

Original language	English (US)
Title of host publication	European Conference on Circuit Theory and Design 2007, ECCTD 2007
Publisher	IEEE Computer Society
Pages	356-359
Number of pages	4
ISBN (Print)	1424413427, 9781424413423
DOIs	https://doi.org/10.1109/ECCTD.2007.4529606
State	Published - 2007
Externally published	Yes
Event	European Conference on Circuit Theory and Design 2007, ECCTD 2007 - Seville, Spain Duration: Aug 26 2007 → Aug 30 2007

Publication series

Name	European Conference on Circuit Theory and Design 2007, ECCTD 2007

Other

Other	European Conference on Circuit Theory and Design 2007, ECCTD 2007
Country/Territory	Spain
City	Seville
Period	8/26/07 → 8/30/07

ASJC Scopus subject areas

Computational Theory and Mathematics
Electrical and Electronic Engineering

Access to Document

10.1109/ECCTD.2007.4529606

Cite this

Lee, D., Song, J., Shin, J., Hwang, S., Song, M., & Wysocki, T. (2007). Design of a 1.8V 8-bit 500MSPS Folding-interpolation CMOS A/D converter with a folder averaging technique. In European Conference on Circuit Theory and Design 2007, ECCTD 2007 (pp. 356-359). Article 4529606 (European Conference on Circuit Theory and Design 2007, ECCTD 2007). IEEE Computer Society. https://doi.org/10.1109/ECCTD.2007.4529606

Design of a 1.8V 8-bit 500MSPS Folding-interpolation CMOS A/D converter with a folder averaging technique. / Lee, Dongjin; Song, Jaewon; Shin, Jongha et al.
European Conference on Circuit Theory and Design 2007, ECCTD 2007. IEEE Computer Society, 2007. p. 356-359 4529606 (European Conference on Circuit Theory and Design 2007, ECCTD 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, D, Song, J, Shin, J, Hwang, S, Song, M & Wysocki, T 2007, Design of a 1.8V 8-bit 500MSPS Folding-interpolation CMOS A/D converter with a folder averaging technique. in European Conference on Circuit Theory and Design 2007, ECCTD 2007., 4529606, European Conference on Circuit Theory and Design 2007, ECCTD 2007, IEEE Computer Society, pp. 356-359, European Conference on Circuit Theory and Design 2007, ECCTD 2007, Seville, Spain, 8/26/07. https://doi.org/10.1109/ECCTD.2007.4529606

Lee D, Song J, Shin J, Hwang S, Song M, Wysocki T. Design of a 1.8V 8-bit 500MSPS Folding-interpolation CMOS A/D converter with a folder averaging technique. In European Conference on Circuit Theory and Design 2007, ECCTD 2007. IEEE Computer Society. 2007. p. 356-359. 4529606. (European Conference on Circuit Theory and Design 2007, ECCTD 2007). doi: 10.1109/ECCTD.2007.4529606

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abstract = "In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500MSPS at 1.8V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.79mm 2 and it consumes about 200mW at 1.8V power supply. The DNL and INL are within ±0.6/±0.6LSB, respectively. The measured result of SNDR is 47.05dB.",

author = "Dongjin Lee and Jaewon Song and Jongha Shin and Sanghoon Hwang and Minkyu Song and Tad Wysocki",

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doi = "10.1109/ECCTD.2007.4529606",

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AU - Song, Minkyu

AU - Wysocki, Tad

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AB - In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500MSPS at 1.8V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.79mm 2 and it consumes about 200mW at 1.8V power supply. The DNL and INL are within ±0.6/±0.6LSB, respectively. The measured result of SNDR is 47.05dB.

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Design of a 1.8V 8-bit 500MSPS Folding-interpolation CMOS A/D converter with a folder averaging technique

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