Abstract
In Vijayan and Tsay proposed a topological constraint based approach for finding an floor plan with minimal area of a set of blocks from a relative placement. In this paper, we propose a new floor planning algorithm by modifying the constraint based approach. The new algorithm reduces the size of the final layout by removing all redundant edges rather than removing only the edges on the critical path. Our experiments showed that the improved algorithm provides an average of 20 percent better reduction in the total layout area.
| Original language | English (US) |
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| Title of host publication | Midwest Symposium on Circuits and Systems |
| Place of Publication | Piscataway, NJ, United States |
| Publisher | IEEE |
| Pages | 310-313 |
| Number of pages | 4 |
| Volume | 1 |
| State | Published - 1995 |
| Event | Proceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Rio de Janeiro, Braz Duration: Aug 13 1995 → Aug 16 1995 |
Other
| Other | Proceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems. Part 1 (of 2) |
|---|---|
| City | Rio de Janeiro, Braz |
| Period | 8/13/95 → 8/16/95 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials