Improved floor planning algorithm using topological constraint reduction

Blaine A. Asato, Hesham H. Ali

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

In Vijayan and Tsay proposed a topological constraint based approach for finding an floor plan with minimal area of a set of blocks from a relative placement. In this paper, we propose a new floor planning algorithm by modifying the constraint based approach. The new algorithm reduces the size of the final layout by removing all redundant edges rather than removing only the edges on the critical path. Our experiments showed that the improved algorithm provides an average of 20 percent better reduction in the total layout area.

Original languageEnglish (US)
Title of host publicationMidwest Symposium on Circuits and Systems
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages310-313
Number of pages4
Volume1
StatePublished - 1995
EventProceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Rio de Janeiro, Braz
Duration: Aug 13 1995Aug 16 1995

Other

OtherProceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems. Part 1 (of 2)
CityRio de Janeiro, Braz
Period8/13/958/16/95

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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    Asato, B. A., & Ali, H. H. (1995). Improved floor planning algorithm using topological constraint reduction. In Midwest Symposium on Circuits and Systems (Vol. 1, pp. 310-313). IEEE.