Abstract
Although the notion of the parallelism in multidimensional applications has existed for a long time, it is so far unknown what the bound (if any) of inter-iteration parallelism in multirate multidimensional digital signal processing (DSP) algorithms is, and whether the maximum inter-iteration parallelism can be achieved for arbitrary multirate data flow algorithms. This paper explores the bound of inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms and proves that this parallelism can always be achieved in hardware system given the availability of a large number of processors and the interconnections between them.
Original language | English (US) |
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Pages (from-to) | 106-125 |
Number of pages | 20 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 13 |
Issue number | 1 |
DOIs | |
State | Published - Jan 2005 |
Keywords
- Inter-iteration parallelism
- Multidimensional data flow graph
- Multidimensional unfolding
- Multirate signal processing
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering