On exploring inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms

Dongming Peng; Mi Lu

doi:10.1109/TVLSI.2004.840401

On exploring inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms

Dongming Peng, Mi Lu

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

Although the notion of the parallelism in multidimensional applications has existed for a long time, it is so far unknown what the bound (if any) of inter-iteration parallelism in multirate multidimensional digital signal processing (DSP) algorithms is, and whether the maximum inter-iteration parallelism can be achieved for arbitrary multirate data flow algorithms. This paper explores the bound of inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms and proves that this parallelism can always be achieved in hardware system given the availability of a large number of processors and the interconnections between them.

Original language	English (US)
Pages (from-to)	106-125
Number of pages	20
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	13
Issue number	1
DOIs	https://doi.org/10.1109/TVLSI.2004.840401
State	Published - Jan 2005

Keywords

Inter-iteration parallelism
Multidimensional data flow graph
Multidimensional unfolding
Multirate signal processing

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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@article{d502d77ba70742de93481037328f07fa,

title = "On exploring inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms",

abstract = "Although the notion of the parallelism in multidimensional applications has existed for a long time, it is so far unknown what the bound (if any) of inter-iteration parallelism in multirate multidimensional digital signal processing (DSP) algorithms is, and whether the maximum inter-iteration parallelism can be achieved for arbitrary multirate data flow algorithms. This paper explores the bound of inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms and proves that this parallelism can always be achieved in hardware system given the availability of a large number of processors and the interconnections between them.",

keywords = "Inter-iteration parallelism, Multidimensional data flow graph, Multidimensional unfolding, Multirate signal processing",

author = "Dongming Peng and Mi Lu",

year = "2005",

month = jan,

doi = "10.1109/TVLSI.2004.840401",

language = "English (US)",

volume = "13",

pages = "106--125",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - On exploring inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms

AU - Peng, Dongming

AU - Lu, Mi

PY - 2005/1

Y1 - 2005/1

N2 - Although the notion of the parallelism in multidimensional applications has existed for a long time, it is so far unknown what the bound (if any) of inter-iteration parallelism in multirate multidimensional digital signal processing (DSP) algorithms is, and whether the maximum inter-iteration parallelism can be achieved for arbitrary multirate data flow algorithms. This paper explores the bound of inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms and proves that this parallelism can always be achieved in hardware system given the availability of a large number of processors and the interconnections between them.

AB - Although the notion of the parallelism in multidimensional applications has existed for a long time, it is so far unknown what the bound (if any) of inter-iteration parallelism in multirate multidimensional digital signal processing (DSP) algorithms is, and whether the maximum inter-iteration parallelism can be achieved for arbitrary multirate data flow algorithms. This paper explores the bound of inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms and proves that this parallelism can always be achieved in hardware system given the availability of a large number of processors and the interconnections between them.

KW - Inter-iteration parallelism

KW - Multidimensional data flow graph

KW - Multidimensional unfolding

KW - Multirate signal processing

UR - http://www.scopus.com/inward/record.url?scp=13144277609&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=13144277609&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2004.840401

DO - 10.1109/TVLSI.2004.840401

M3 - Article

AN - SCOPUS:13144277609

VL - 13

SP - 106

EP - 125

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 1

ER -