Structured bit-interleaved LDPC codes for MLC flash memory

Kathryn Haymaker, Christine A. Kelley

Research output: Contribution to journalArticle

13 Scopus citations

Abstract

Due to a structural feature in the programming process of MLC (two bits per cell) and TLC (three bits per cell) flash memory, the majority of errors that occur are single-bit errors. Moreover, the voltages used to store the bits typically result in different bit error probabilities for the two or three types of bits. In this work we analyze binary regular LDPC codes in the standard bit-interleaved coded modulation implementation, assuming different probabilities on the bits, to determine what ratio of each type of bit should be connected at the check nodes to improve the decoding threshold. We then propose a construction of nonbinary LDPC codes using their binary images, resulting in check node types that come close to these optimal ratios.

Original languageEnglish (US)
Article number6804932
Pages (from-to)870-879
Number of pages10
JournalIEEE Journal on Selected Areas in Communications
Volume32
Issue number5
DOIs
Publication statusPublished - May 2014

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Keywords

  • Parity check codes
  • bipartite graph
  • iterative decoding

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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