Structured graph models: An tool for VLSI design efficient

M. Ancona, K. S. Bagga, E. Bruzzone, L. De Floriani, J. S. Deogun

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Hierarchical graph models are a powerful tool for describing VLSI circuits. They combine the representation of a hierarchical decomposition of a circuit with a graph description of its topological structure in terms of components and connections. Structured Graphs are an example of such models. In this paper we consider the graph-theoretic problems of spanning trees and Steiner trees in structured graphs. These have connections with the global routing problems in VLSI circuits.

Original languageEnglish (US)
Title of host publicationComputing in the 1990's - 1st Great Lakes Computer Science Conference, Proceedings
EditorsNaveed A. Sherwani, Elise de Doncker, John A. Kapenga
PublisherSpringer Verlag
Number of pages6
ISBN (Print)9780387976280
StatePublished - 1991
Externally publishedYes
Event1st Great Lakes Computer Science Conference, 1989 - Kalamazoo, United States
Duration: Oct 18 1989Oct 20 1989

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume507 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other1st Great Lakes Computer Science Conference, 1989
Country/TerritoryUnited States

ASJC Scopus subject areas

  • Theoretical Computer Science
  • General Computer Science


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