Towards a new quasigroup block cipher for a single-chip FPGA implementation

William Mahoney; Abhishek Parakh

doi:10.1109/ICCCN.2015.7288479

Towards a new quasigroup block cipher for a single-chip FPGA implementation

William Mahoney, Abhishek Parakh

Cybersecurity

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

In earlier work the authors reported on methods they investigated to implement quasigroup block encryption in hardware, with an emphasis on low cost. The aim was to design and deliver a hardware design solution that was inexpensive but did not sacrifice encryption security; the desired target for the design is low-bandwidth, low-cost areas such as Supervisory Control And Data Acquisition (SCADA) systems. Here the authors report on further refinements of this design with the aim of making a single-chip solution.

Original language	English (US)
Title of host publication	24th International Conference on Computer Communications and Networks, ICCCN 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479999644
DOIs	https://doi.org/10.1109/ICCCN.2015.7288479
State	Published - Oct 2 2015
Event	24th International Conference on Computer Communications and Networks, ICCCN 2015 - Las Vegas, United States Duration: Aug 3 2015 → Aug 6 2015

Publication series

Name	Proceedings - International Conference on Computer Communications and Networks, ICCCN
Volume	2015-October
ISSN (Print)	1095-2055

Other

Other	24th International Conference on Computer Communications and Networks, ICCCN 2015
Country/Territory	United States
City	Las Vegas
Period	8/3/15 → 8/6/15

Keywords

FPGA
Latin Squares
Quasigroup
SCADA

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture
Software

Access to Document

10.1109/ICCCN.2015.7288479

Cite this

Mahoney, W., & Parakh, A. (2015). Towards a new quasigroup block cipher for a single-chip FPGA implementation. In 24th International Conference on Computer Communications and Networks, ICCCN 2015 Article 7288479 (Proceedings - International Conference on Computer Communications and Networks, ICCCN; Vol. 2015-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCCN.2015.7288479

Towards a new quasigroup block cipher for a single-chip FPGA implementation. / Mahoney, William; Parakh, Abhishek.
24th International Conference on Computer Communications and Networks, ICCCN 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7288479 (Proceedings - International Conference on Computer Communications and Networks, ICCCN; Vol. 2015-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Mahoney, W & Parakh, A 2015, Towards a new quasigroup block cipher for a single-chip FPGA implementation. in 24th International Conference on Computer Communications and Networks, ICCCN 2015., 7288479, Proceedings - International Conference on Computer Communications and Networks, ICCCN, vol. 2015-October, Institute of Electrical and Electronics Engineers Inc., 24th International Conference on Computer Communications and Networks, ICCCN 2015, Las Vegas, United States, 8/3/15. https://doi.org/10.1109/ICCCN.2015.7288479

Mahoney W, Parakh A. Towards a new quasigroup block cipher for a single-chip FPGA implementation. In 24th International Conference on Computer Communications and Networks, ICCCN 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7288479. (Proceedings - International Conference on Computer Communications and Networks, ICCCN). doi: 10.1109/ICCCN.2015.7288479

@inproceedings{8d843fa4d24c4bf2b98a841f22b36184,

title = "Towards a new quasigroup block cipher for a single-chip FPGA implementation",

abstract = "In earlier work the authors reported on methods they investigated to implement quasigroup block encryption in hardware, with an emphasis on low cost. The aim was to design and deliver a hardware design solution that was inexpensive but did not sacrifice encryption security; the desired target for the design is low-bandwidth, low-cost areas such as Supervisory Control And Data Acquisition (SCADA) systems. Here the authors report on further refinements of this design with the aim of making a single-chip solution.",

keywords = "FPGA, Latin Squares, Quasigroup, SCADA",

author = "William Mahoney and Abhishek Parakh",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 24th International Conference on Computer Communications and Networks, ICCCN 2015 ; Conference date: 03-08-2015 Through 06-08-2015",

year = "2015",

month = oct,

day = "2",

doi = "10.1109/ICCCN.2015.7288479",

language = "English (US)",

series = "Proceedings - International Conference on Computer Communications and Networks, ICCCN",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "24th International Conference on Computer Communications and Networks, ICCCN 2015",

}

TY - GEN

T1 - Towards a new quasigroup block cipher for a single-chip FPGA implementation

AU - Mahoney, William

AU - Parakh, Abhishek

PY - 2015/10/2

Y1 - 2015/10/2

N2 - In earlier work the authors reported on methods they investigated to implement quasigroup block encryption in hardware, with an emphasis on low cost. The aim was to design and deliver a hardware design solution that was inexpensive but did not sacrifice encryption security; the desired target for the design is low-bandwidth, low-cost areas such as Supervisory Control And Data Acquisition (SCADA) systems. Here the authors report on further refinements of this design with the aim of making a single-chip solution.

AB - In earlier work the authors reported on methods they investigated to implement quasigroup block encryption in hardware, with an emphasis on low cost. The aim was to design and deliver a hardware design solution that was inexpensive but did not sacrifice encryption security; the desired target for the design is low-bandwidth, low-cost areas such as Supervisory Control And Data Acquisition (SCADA) systems. Here the authors report on further refinements of this design with the aim of making a single-chip solution.

KW - FPGA

KW - Latin Squares

KW - Quasigroup

KW - SCADA

UR - http://www.scopus.com/inward/record.url?scp=84959386348&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84959386348&partnerID=8YFLogxK

U2 - 10.1109/ICCCN.2015.7288479

DO - 10.1109/ICCCN.2015.7288479

M3 - Conference contribution

AN - SCOPUS:84959386348

T3 - Proceedings - International Conference on Computer Communications and Networks, ICCCN

BT - 24th International Conference on Computer Communications and Networks, ICCCN 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 24th International Conference on Computer Communications and Networks, ICCCN 2015

Y2 - 3 August 2015 through 6 August 2015

ER -

Towards a new quasigroup block cipher for a single-chip FPGA implementation

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this